.TITLE	MPENT
	.IDENT	/03.03/
 
;
; Copyright (c) 1995-1999 by Mentec, Inc., U.S.A.
; All rights reserved
;
; THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY ONLY BE USED
; OR COPIED IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE.
;
; K. E. KINNEAR 26-JAN-79
;
; MULTIPROCESSOR CPU STARTUP PROCESSING
;
; MODIFIED BY:
;
;	J. W. BERZLE
;
; MODIFIED FOR RSX-11M-PLUS V4.4 BY:
;
;	D. T. CARROLL	30-MAY-1992	03.01
;
;	   DC103 -- Insure the clock vector is set correctly
;		    for the P-clock when an L-clock is in use
;
; MODIFIED FOR RSX-11M-PLUS V4.5 BY:
;
;	D. CARROLL	17-JUN-1993	03.02
;		DC227 -- Handle possible UNIBUS memory configuration
;
; Modified for RSX-11M-PLUS V4.6 by:
;
;	D. Carroll	18-Oct-1995	03.03
;		DC404 - Include PSECT definitions to allow extention of
;			ICB pool
;
;
; THE FOLLOWING CODE IS DUPLICATED IN INITL.MAC, AND IS USED TO SET
; THE MAPPING FOR STARTUP OF A CPU.  ANY MODIFICATIONS HERE MUST BE
; REFLECTED IN THE SIMILAR CODE IN INITL.
;

;
; MACRO LIBRARY CALLS
;

	.MCALL	BGCK$A
										;DC404
	.IIF	DF,K$$DAS&I$$CBP,	.PSECT	EXEC1				;DC404

	.IF DF	M$$PRO

$PENT::	MOV	#PMODE!PR7,PS	;;;INIT MODE BITS & LOCK OUT INTERRUPTS
	MOV	#$STACK-20,SP	;;;SET UP KERNEL STACK POINTER
	MOV	#KINAR0,R5	;;;INIT POINTER TO MAPPING REGISTERS
	CLR	R1		;;;INIT I SPACE MEMORY OFFSET


	.IF DF	K$$DAS

	MOV	$SCMOF,R2	;;;INIT D SPACE MEMORY OFFSET
	BNE	5$		;;;IF NE DATA SPACE LOADED
	TST	$URMST		;;;IS THIS FROM INITL?
	BNE	5$		;;;IF NE NO -- REGULAR CPU ENTRY
	MOV	#$MESS1,R4	;;;SPECIFY DATA SPACE NOT LOADED MESSAGE
	CALL	$FATAL		;;;PRINT OUT FATAL ERROR MESSAGE
	BGCK$A	BF.MP,BE.NDS,HALT ;;;DATA SPACE NOT LOADED
5$:	SUB	#200,R2		;;;

	.IFTF

6$:				;;;REFERENCE LABEL

	.IFT

	MOV	#77406,KDSDR0-KINAR0(R5) ;;;SET D SPACE 4K RW
	MOV	R2,KDSAR0-KINAR0(R5) ;;;SET D SPACE APR OFFSET
	ADD	#200,R2		;;;ADVANCE D SPACE APR OFFSET
	MOV	#77402,KINDR0-KINAR0(R5) ;;;SET I SPACE 4K RO

	.IFF

	MOV	#77406,KINDR0-KINAR0(R5) ;;;SET I SPACE 4K RW

	.IFTF

	MOV	R1,(R5)+	;;;SET I SPACE APR OFFSET
	ADD	#200,R1		;;;ADVANCE I SPACE OFFSET
	CMP	R5,#KINAR7	;;;DONE YET?
	BLOS	6$		;;;IF LOS NO
	MOV	#177600,KINAR7	;;;SET UP I/O PAGE MAPPING

	.IFT

	MOV	#177600,KDSAR6+2 ;;;SET UP D-SPACE MAPPING TOO
	CLR	(R5)		;;;CLEAR DSPACE APR0 OFFSET

	.ENDC


	.IF DF	K$$DAS!M$$EXT!S$$LIB

	MOV	#S3$BTS,SR3	;;;SET UP SR3

	.ENDC


	INC	SR0		;;;START MEMORY MAPPING

;
; WE HAVE, WITH THE LAST INSTRUCTION, JUST CHANGE THE MAPPING
; THROUGH WHICH THE CPU IS FETCHING INSTRUCTIONS.  IF WE ARE
; ON CPA THEN NO ACTUAL CHANGE WAS MADE, BUT IF ON SOME OTHER
; CPU, THEN WE ARE NOW FETCHING INSTRUCTIONS FROM THE NEW MAPPING.
;

	TST	$URMST		;;;WERE WE CALLED FROM INITL?
	BNE	7$		;;;IF NE NO -- DON'T RETURN THERE
	JMP	$INITM		;;;RETURN BACK TO INITL
7$:	MOV	#PARTB,R5	;;;SET RETURN ADDRESS
	MOV	#$NS0,SP	;;;SET UP STACK FOR CPU STARTUP
$MAPCP::MOV	$IICTB,R1	;;;GET AN IIST KRB (ANY ONE)
	MOV	#9$,-(SP)	;;;SET UP RETURN FROM $SGFIN
	TST	$URMST		;;;IS THIS THE FIRST CPU?
	BNE	5$		;;;IF NE NO -- IIST MUST BE THERE
				;;;SO DONT $SGFIN ON CPA'S VECTORS
	CALL	$SGFIN		;;;ON CPA, TRAP NON-EXISTANT IIST REGS
5$:	MOV	@(R1),R0	;;;GET IIST REGISTER (IF ANY)
	BCS	8$		;;;IF CS NO REGISTER -- CPA FORCED
	SWAB	R0		;;;PUT CPU NUMBER IN LOW BYTE
	BIC	#177770,R0	;;;CLEAR EXTRANEOUS BITS
	CMPB	R0,$NCPU	;;;TOO HIGH A PROCESSOR?
	BGE	8$		;;;IF GT YES -- MAKE CPA AGAIN
	ASL	R0		;;;MAKE CPU INTO WORD INDEX
	MOV	$IICTB(R0),R1	;;;GET PROPER IIST KRB ADDRESS
	BIC	#KS.OFL,K.STS(R1) ;;;CLEAR OFFLINE BIT FOR THIS IIST
	MOV	(R1),$PWCSR	;;;SAVE IIST CSR FOR POWER UP ROUTINE
				;;;IN CPA'S CPU SPECIFIC AREA
	RETURN
8$:	CLR	R0		;;;FORCE TO CPA
	RETURN
9$:	MOV	$K6TAB(R0),KINAR0 ;;;SET UP LOCAL MAPPING


	.IF DF	K$$DAS

	MOV	$K6TAB(R0),KDSAR0 ;;;SET UP FIRST D SPACE PAR

	.ENDC


	MOV	#$STACK-20,SP	;;;SET UP PROPER STACK AREA
	MOV	R5,-(SP)	;;;MAKE INTO SUBROUTINE CALL


	.IF DF	X$$DBT

	BIT	$CPBIT,$XDTFL	;;;HAS XDT BEEN INITIALIZED ON THIS CPU?
	BNE	12$		;;;IF NE YES
	CALL	$XDTIN		;;;INITIALIZE XDT
12$:	MOV	#PMODE!PR7,PS	;;;SET UP MODE BITS AFTER XDT SCREWS IT

	.ENDC


;
; INITIALIZE THE UNIBUS MAPPING REGISTERS ON THIS PROCESSOR IF IT IS
; A PDP-11/7X TYPE PROCESSOR.
;


	CALL	$SGFIN		;;;CATCH MEMORY FAULTS AND SET CARRY
	MOV	#UBMPR,R0	;;;POINT TO FIRST UNIBUS MAP REGISTER
	BIC	#HF.UBM,$HFMSK	;;;ASSUME NO UMRS
	TST	(R0)		;;;ARE UMRS PRESENT?
	BCS	20$		;;;IF CS NO
	BIS	#HF.UBM,$HFMSK	;;;INDICATE THAT UMRS ARE PRESENT
	MOV	KINAR0,R3	;;;GET MAPPING OF VIRTUAL ZERO
	CLR	R2		;;;CLEAR HIGH PART OF UMR VALUE
	ASHC	#6,R2		;;;CONVERT TO DOUBLE WORD BYTE OFFSET
	.IF DF	P$$D74
	BIS	#100000,R2	;;; FORCE CACHE BYPASS ON UMR
	.ENDC	;DF,P$$D74
	MOV	R3,(R0)+	;;;SET UP LOW HALF OF UMR
	MOV	R2,(R0)+	;;;AND HIGH HALF OF UMR


	.IF DF	K$$DAS

	MOV	$SCMOF,R3	;;;PICK UP OFFSET TO DATA SPACE
	CLR	R2		;;;SET FOR CONVERSION
	ASHC	#6,R2		;;;CONVERT TO DOUBLE WORD BYTE OFFSET
	MOV	#4,R1		;;;SET COUNT OF UMR'S TO LOAD
	.IF DF	P$$D74
	BIS	#100000,R2	;;; INCLUDE CACHE BYPASS AS WELL
	.ENDC	;DF,P$$D74
15$:	MOV	R3,(R0)+	;;;LOAD LOW 16 BITS OF ADDRESS
	MOV	R2,(R0)+	;;;LOAD HIGH 6 BITS OF ADDRESS
	ADD	#20000,R3	;;;BUMP ADDRESS BY 4K WORDS
	ADC	R2		;;;...
	SOB	R1,15$		;;;LOOP FOR ALL UMRS

	.IFF

	CLR	R1		;;;INIT UMR OFFSET
	MOV	#4,R2		;;;SET NUMBER OF REGISTER PAIRS TO LOAD
15$:	ADD	#20000,R1	;;;ADVANCE UMR OFFSET
	MOV	R1,(R0)+	;;;LOAD LOW 16 BITS OF ADDRESS
	.IF DF	P$$D74
	MOV	#100000,(R0)+	;;;INIT WITH CACHE BYPASS SET
	.IFF	;
	CLR	(R0)+		;;;CLEAR HIGH 6 BITS OF ADDRESS
	.ENDC	;DF,P$$D74
	SOB	R2,15$		;;;LOOP FOR ALL UMRS

	.ENDC

	.IF DF U$$BME

	MOV	#UBMPR+174,R1	;;; SET LAST UMR ADDRESS
17$:	MOV	#160000,(R0)+	;;; ZERO OUT A UMR
	BCS	18$		;;; IF CS, UMR NOT PRESENT
	.IF DF	P$$D74		;;; 11/74 SYSTEM?
	MOV	#100077,(R0)+	;;; AND MAP TO NEVER, NEVER LAND
	.IFF	;
	MOV	#77,(R0)+	;;; AND MAP TO NEVER, NEVER LAND
	.ENDC	;DF,P$$D74
	CMP	R1,R0		;;; DONE ALL OF THEM?
	BNE	17$		;;; NOPE, CONTINUE

18$:	SUB	R0,R1		;;; DETERMINE HOW MANY UMRS EXIST
	ADD	#4,R1		;;; AND ACCOUNT FOR THE LAST UMR
	MOV	R0,$UBUMR+M.UMRA	;;; SET THE FIRST NXM UMR
	MOV	R1,$UBUMR+M.UMRN	;;; AND THE COUNT

	.ENDC	;DF,U$$BME

20$:	RETURN			;;;

;
; SCAN PARITY MEMORY CSR REGISTERS AND CREATE TABLE FOR THIS CPU
;

PARTB:	MOV	#$DIRXT,-(SP)	;;;EXIT FINALLY TO $DIRXT
	CALL	$SGFIN		;;;CATCH TRAPS TO 4 AND SET CARRY
	MOV	#$PARTB,R0	;;;GET ADDRESS OF PARITY CSR TABLE
	MOV	R0,R1		;;;COPY ADDRESS OF TABLE
	MOV	#1,(R1)+	;;;INSERT A ONE IN FIRST TABLE ENTRY
	MOV	#$CSRTB,R4	;;;GET ADDRESS OF CSR TABLE
16$:	MOVB	(R4)+,R3	;;;GET NUMBER OF CSR'S TO SET UP
	BEQ	22$		;;;IF EQ DONE
	CLR	R2		;;;INITIALIZE CSR ADDRESS
	BISB	(R4)+,R2	;;;CALCULATE CSR ADDRESS
	SWAB	R2		;;;GET HIGH BYTE OF CSR ADDRESS
	BISB	(R4)+,R2	;;;GET LOW BYTE OF CSR ADDRESS
17$:	TST	(R2)		;;;CSR PRESENT?
	BCS	19$		;;;IF CS NO
	MOV	R2,(R1)+	;;;SAVE CSR ADDRESS
	BR	20$		;;;
19$:	MOV	R0,(R1)+	;;;POINT TO FIRST WORD OF TABLE
20$:	ADD	#2,R2		;;;POINT TO NEXT CSR
	SOB	R3,17$		;;;LOOP UNTIL DONE
	BR	16$		;;;CONTINUE THROUGH THE REST OF THE TABLE

;
; CLOCK INITIALIZATION -- CLOCKS ON ALL SECONDARY PROCESSORS MUST
; BE THE SAME TYPE AS THE PRIMARY PROCESSOR (I.E. EITHER ALL KW11-L
; OR KW11-P) OR WE WILL HALT
;

22$:	TST	@$CKCSR		;;;IS THE CLOCK AVAILABLE
	BCC	25$		;;;IF CC YES
	BGCK$A	BF.MP,BE.NCK,HALT ;;;NO -- CLOCK UNAVAILABLE
25$:	CMP	#172540,$CKCSR	;;;IS IT KW11-P
	BNE	30$		;;;IF NE NO
	MOV	#$CKINT,@#104	;;;SET UP KW11-P INTERRUPT
	.IF DF	E$$NSI
	MOV	#$NS1,@#100	;;;DISABLE KW11-L INTERRUPT
	.IFF	;E$$NSI
	MOV	#$NONSI,@#100	;;;DISABLE KW11-L INTERRUPT
	.ENDC	;E$$NSI
	BR	40$
30$:	.IF DF	E$$NSI
	MOV	#$NS1,@#104	;;;DISABLE KW11-P INTERRUPT
	.IFF	;E$$NSI
	MOV	#$NONSI,@#104	;;;DISABLE KW11-P INTERRUPT
	.ENDC	;E$$NSI
	MOV	#$CKINT,@#100	;;;SET UP KW11-L INTERRUPT
	TST	$CKCSR		;;;DOES THE CLOCK HAVE A CSR?
	BEQ	45$		;;;IF EQ NO
40$:	MOV	$CKLDC,@$CKCNT	;;;SETUP CLOCK COUNT REGISTER
	MOV	#K$$IEN,@$CKCSR	;;;START CLOCK
45$:				;;;REFERENCE SYMBOL


	.IF DF	F$$LPP

	TST	PIRQ		;;;IS THERE A PIRQ REGISTER
	BCS	50$		;;;IF CS NO
	MOV	#$FPPRQ,@#240	;;;SET UP PIRQ VECTOR
	MOV	#$FPPR8,@#244	;;;SET UP FLOATING POINT EXCEPTION VEC
50$:				;;;REFERENCE LABEL

	.ENDC


; MOVE $HFMSK FROM CPA'S LOWCR INTO THAT OF THE PROCESSOR COMING ONLINE

	MOV	KISAR6,-(SP)	;;;SAVE CURRENT KERNEL MAPPING
	CLR	KISAR6		;;;MAP TO CPA'S LOW CORE AREA
	MOV	$HFMSK+140000,$HFMSK ;;;PROPAGATE TO NEW PROCESSOR
	MOV	(SP)+,KISAR6	;;;RESTORE KERNEL MAPPING


	LOCK$	$EXECL,WAIT
	LOCK$	$IIFNL,SPIN	;;;LOCK THE MULTIPROCESSOR FUNCTION TBL
	BIC	#MP.STP,@$MPSWT	;;;CLEAR OUT OUR STOP BIT
	ULOCK$	$IIFNL,SPIN	;;;UNLOCK THE FN TABLE
	CALL	$CPNIT		;;;START UP PROCESSOR


	.IF NDF	X$$DBT

$XDTIN::			;;;REFERENCE LABEL -- NULL SUBROUTINE

	.IFTF

	RETURN

	.ENDC



	.ENDC


	.END